...for the sake of fostering more interaction between fellow code monkeys, as this forum seems almost eerily quiet...
What does everyone think of the upcoming 64-bit processors from both Intel & AMD? Apart from the fact that they're good.
I've only had the oppurtunity to check out AMD's x86-64, which seems pretty sweet - flat memory addressing & SSE2 style extensions are a great step forward, and crucial if AMD is to catch up to Intel.
Or is assembly so dead that, as programmers, they could release the next-generation of PC's as 4-bit beasts, laugh in the face of L1 & L2 cache, and we wouldn't bat an eyelid?
More inane topics to follow every week until somebody talks to me! Anybody! Please!
-Soul
Actually the Athlon, AMD K6 and the Pentium Pro onwards all had internal RISC Machines. The Athlon's was based of DEC's Alpha same as the Pentium Pro.. although the Athlon copied the EV6 Bus plus implemented a more super scalar FPU compared to the Pentium's PRO (and derivates).
The K6 was a NexGen CPU in disgused which makes it First x86 compatible CPU that used a RISC core.
I played poker with a Tarot deck the other night. I got a full house and four people died.
--Steven Wright.
Internal RISC - aren't you just talking about micro-ops there? Essentially its still a CISC architecture for all those chips, except that they decode the more complex instructions into a series of small fetch-compute-store micro-ops (or micro instructions), hence the RISCness of it.
I believe its not the same as a pure RISc processor that interprets CISC 80x86 instructions like the P4.
The P4 uses the same technique as the NexGen K5, in fact there where earlier attemps made by IBM. They wanted the PowerPC to succeed so badly it made and botched to make it handle x86 code.
Rememeber the Transmeta CPU does the same thing except on Software, and it's VLIW processor akin to the Itanium.
I played poker with a Tarot deck the other night. I got a full house and four people died.
--Steven Wright.
I think if you read the IA-32 Intel documentation it states that the P4 still uses a CISC decoder (micro-ops as they call them) seeing as it uses the intel NetBurst micro-architecture which is basically just a multi-threaded pipeline specification with some catch phrases and also that out-of-step execution which I like the sound of.
As for the IA-64 v x86-64, I've got no definite idea, but it definitely looks like AMD have had to play a bit of catch up lately, but look to have the 64 bit processor of the future.
SSE2 is important, and 64bit addressing is good to hear as well as we start to breach that 4 gig of memory that we used to think was oh so much.
As far as assembly concerns go, I imagine it's going to screw alot of old code up in terms of efficiency, and it's going to give compiler and OS developers a headache and a half :)
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Anyone here got large sums of assembly language code in their programs? I mean - can someone clear up this misconception if it is one - but how on earth is the IA-64 going to cover all the old packed instructions like SSE/MMX has, and things like that, if it's a RISC architecture? Seeing as it's going to have (virtually) 127 integer registers surely we are going to have to kill off any previous MMX/SSE/3DNOW assembly code we wrote and rewrite a bunch of "implicitly parellel processed" C/C++ code or whatever language you use? This is obviously a pretty big pain in the arse if you've wrote a very large backend that has some machine dependent code in it for the purposes of speed.
How good are the compilers going to be at taking advantage of these things? Sure it's a tired question to say "the compiler isn't fast enough" but surely we were getting pretty good at compilers for the current range of chipsets, we'd have to completely change the structure of them now to keep up the same level of code efficiency for the IA-64.
And what about the bloating of the compiled code too? Obviously there is the deficit of 64+ bit instructions instead of 32bit, but also the compiled code will be longer too being a RISC architecture having to repeat the same instructions more frequently.
Anyone got a quote on how much L1 and L2 cache we'll get on these chipsets to make up for that?
Personally I'm leaning towards a preference for x86-64 architecure due to backwards compatability.
(cue Spartacus style responses plz? Or don't people attend this forum?)
Snootchie bootchies!
Any off-topic issues send to maitrek@austarmetro.com.au
Being Intel I'd imagine that they'd include the SSE instructions at least, since technically the SSE and SSE2 instructions are made to operate on a vector of data in parallel. I'd say they'd dump MMX since that's what the RISC insturctions would be doing anyway, just much better and much faster.
Also with the instructions, even though its a 64 bit machine, the instruction might only take up about 16 bits in total, including encoding for the different parameters used etc. So most likely you'd also include several parameters within the full 64 bits.
(Oh well, I guess we'll learn more of this in Computer Architecture eh?)
It seems that the IA-32 instruction emulation on the IA-64 chipsets are Pentium III based, meaning MMX is supported and SSE1 and SSE2 when operating in IA-32 instruction set modes.
There seems to be a huge amount of mess when it comes to running in this IS mode in terms of the level of protection and things like that. It's got protected, real, VM86 memory addressing modes and all sorts of register mapping going on. To me it seems like they've really sorta copped out on their plans to create a real RISC architecture. Except of course, for new programs that run purely in the IA-64 mode.
Intel are trying to dig themselves out of a hole they made fifteen years ago and I think it might be a wee bit late.
To me it seems the x86-64 architecture doesn't have the old instruction set emulation...ie - it's fully backwards compatable - don't know for sure though. Although I'm probably AMD biased so don't take my advice.
Snootchie bootchies!
Any off-topic issues send to maitrek@austarmetro.com.au
I'd have to read up on this topic a bit more, perhaps someone could post up the links to the relevant sections for the AMD and Intel 64 bit chips.
Personally It doesn't really matter when they bring our 64 bit chips, I'd be happy with onyl a 32 bit processor still, but that it could also be massively SIMDised, that instead of operating on just one data type at a time it'd have multiple data pipelines that would use data quite quickly. Or maybe perhaps I am thinking of a processor that's a multiprocessor system in one, with multiple pipes that could run multiple threads at once.
Although one thing that we should add is to get away from the 70's chipset architecture, and strive for something more with the times. So far I think only the P4 has gone this way, interpreting the 80x86 commands and running them on its own instruction set.
One nice thing about the 64 bit processors is the amount of ram that could be accessed, mmm, 2^64 bytes of ram... nice.
Blabbing now so I'll stop.